1. Field of the Invention
The invention relates generally to circuit design. More particularly, the invention relates to computer assisted simulation within circuit design.
2. Description of the Related Art
In order to provide for enhanced performance, modern semiconductor circuits utilize metallization structures that typically comprise copper containing conductor layers. The metallization structures also typically comprise generally lower dielectric constant dielectric layers (i.e., low-k, having a dielectric constant less than about 4.0 and typically from about 2.0 to about 4.0) surrounding the copper containing conductor layers. Copper containing materials provide for enhanced conductivity, while the low dielectric constant dielectric materials provide for enhanced speed and inhibited detrimental capacitive effects such as cross-talk. Since many lower dielectric constant dielectric materials are incompatible with copper containing conductor materials, the metallization structures also typically comprise denser and impervious dielectric barrier layers and conductor barrier layers interposed between the copper containing conductor layers and the low dielectric constant dielectric layers.
Metallization schemes within modern integrated circuits often include up to 10-12 metallization levels. Metallization processing typically involves a damascene or a dual damascene method that is intended to preserve planarity while processing. Damascene methods provide for forming a dielectric layer over a substrate. Appropriate vias and trenches are etched into the dielectric layer and they are overfilled with a metallization layer deposited therein. Excess metal is removed utilizing a planarization method.
Given the increased number of metallization layers in modern integrated circuits, topographic variations are common notwithstanding use of planarizing methods. Similarly, as the dimensions of the semiconductor structures within existing and future generations of semiconductor circuits decreases, the tolerances on the photolithography processes used to pattern the features become smaller. The depth of focus associated with the equipment that patterns features on a photosensitive film limits the magnitude of the variation in height or planarity across a semiconductor substrate. If the topography or height variation exceeds this tolerance, then certain patterns across the wafer will be out of focus, leading to errors in the dimensions of the final structures. The errors can be additive, leading to larger topography differences as the number of levels fabricated on a substrate increases.
Methods for analyzing metallization structures (i.e., post silicon processing back end of line (BEOL) structures) within semiconductor chips are known in the art. For example, Filippi, Jr., et al., in U.S. Pub. No. 2005/0086628 A1 teaches a circuit design analysis system and method that includes discretizing a circuit design into a series of pixel elements (i.e., pixels) for further analysis.
Semiconductor structure dimensions will likely continue to decrease, and as a result thereof semiconductor photolithography requirements are thus likely to have more stringent depth-of-focus requirements. Thus, desirable within semiconductor fabrication are additional systems and methods that may be utilized to assist in assuring that semiconductor photolithography processing may be undertaken within expected depth of focus requirements.